; 2022.11.23, RGB1W+DS1W 1-wire
;
INCLUDE				PIOC_INC.ASM
;
; EXTERNAL
VAR_SIZE_L			EQU   SFR_DATA_REG0
VAR_SIZE_H			EQU   SFR_DATA_REG1
VAR_DATA_L			EQU   SFR_DATA_REG0
VAR_DATA_H			EQU   SFR_DATA_REG1
VAR_FLAG			EQU   SFR_DATA_REG2
; INTERNAL
VAR_ADDR_L			EQU   SFR_DATA_REG30
VAR_ADDR_H			EQU   SFR_DATA_REG31
;
; RESET VECTOR
					ORG   0X0000
					DW    0X0000			;RESERVED INFO
					DW    0X0000			;RESERVED ID
;
MCU_START:			NOP
					NOP
					JMP   WAIT_COMMAND
;
					ORG   0X0008
;
; HIGH/LOW DELAY HALF BIT, 28 CYCLES @48M, 14 CYCLES @24M
RGB1W_DLY_HALF:
					NOP
RGB1W_DLY_HALF_B0:
					CALL  RGB1W_DLY_1L
;					CALL  RGB1W_DLY_1L
;					RET
; 1167nS,0x38(56)@48MHz,0x1C(28)@24MHz
; LOW DELAY FOR 1, 14-3 CYCLES @48M, 7-3 CYCLES @24M
RGB1W_DLY_1L:
					NOP
; HIGH DELAY FOR 0, 14-4 CYCLES @48M, 7-4 CYCLES @24M
RGB1W_DLY_0H:
					NOP
PIOC_FREQ_CFG:
					NOP						;FORCE RET IF 24MHz
; LOW DELAY FOR 1 OF BIT0, 14-3-3 CYCLES @48M, 7-3-3 CYCLES @24M
RGB1W_DLY_1L_B0:
					NOP						;FORCE RET IF 24MHz
					NOP
					NOP
					NOP
					NOP
					NOP
					RET
;
					NOP
					NOP
;
; SFR_CTRL_WR: COMMAND
;     01H-20H: RGB WITH SHORT DATA IN SFR, LOW 7 BIT IS TOTAL BYTE
;     88H-FCH: RGB WITH LONG DATA IN CODE RAM, LOW 7 BIT IS NEW SB_BIT_CYCLE
;         41H: DS1W START CONVERT
;         42H: DS1W GET TEMPERATURE
;         43H: DS1W START CONVERT THEN GET TEMPERATURE
;
WAIT_COMMAND:		BTSS  SFR_SYS_CFG,SB_DATA_SW_MR	;WAIT MASTER ACK
					BC    SFR_SYS_CFG,SB_INT_REQ	;CANCEL INTERRUPT IF ACK
					BTSS  SFR_SYS_CFG,SB_DATA_MW_SR	;NEW COMMAND
					JMP   WAIT_COMMAND		;WAIT COMMAND
					BC    SFR_SYS_CFG,SB_INT_REQ	;CANCEL INTERRUPT
					MOV   SFR_CTRL_WR,A		;COMMAND CODE
					MOVA  SFR_INDIR_ADDR2
					CMPZ  0X41,DS1W_CONVERT
					CMPZ  0X42,DS1W_GET_DATA
					CMPZ  0X43,DS1W_CONV_GET
					CMPZ  0X00,CMD_UNKNOWN	;UNKNOWN COMMAND
					CMPL  0X20
					JNC   RGB1W_SHORT		;SHORT DATA IN SFR IF <=0X20
					CMPL  0X60
					JNC   RGB1W_SHORT_1		;SHORT DATA IN SFR IF <=0X60
					CMPL  0X88-1
					JNC   CMD_UNKNOWN		;UNKNOWN COMMAND IF <=0X87
					CMPL  0XFC
					JNC   RGB1W_LONG		;LONG DATA IN CODE RAM IF <=0XFC
					NOP
					NOP
					NOP
					NOP
					NOP
					NOP
					NOP
					NOP
CMD_UNKNOWN:		MOVL  0X01				;ERROR CODE FOR UNKNOWN COMMAND
					JMP   CMD_RETURN
;
DS1W_CONVERT:		NOP
					CALL  START_TEMPERAT
					JMP   CMD_RETURN
;
DS1W_CONV_GET:		NOP
					CALL  START_TEMPERAT
					JNZ   CMD_RETURN		;FAILED
					MOVIA 75				;750mS
DS1W_WAIT_10MS:		MOVIP 40				;40*250=10mS
DS1W_WAIT_250US:	CALL  DELAY_250US		;250uS
					DEC   SFR_INDIR_ADDR
					JNZ   DS1W_WAIT_250US
					DEC   SFR_INDIR_ADDR2
					JNZ   DS1W_WAIT_10MS
;					JMP   DS1W_GET_DATA
;
DS1W_GET_DATA:		NOP
					CALL  READ_TEMPERAT
					JMP   CMD_RETURN
;
; RGB WITH SHORT DATA IN SFR, SOFTWARE ENCODE
RGB1W_SHORT:		NOP
					CLR   SFR_BIT_CYCLE
					BC    SFR_PORT_IO,SB_PORT_OUT0	;DEFAULT OUTPUT LOW
					BS    SFR_PORT_DIR,SB_PORT_DIR0
					CLR   SFR_BIT_CONFIG
					MOVL  0X06				;ERROR CODE FOR PIN RX HIGH
					BTSC  SFR_PORT_IO,SB_PORT_IN0	;PIN LOW
					JMP   CMD_RETURN		;PIN HIGH
					MOV   SFR_INDIR_ADDR2,A
					MOVA  SFR_INDIR_ADDR	;TOTAL BYTE
					MOVIA SFR_DATA_REG0		;DATA BUFFER START ADDRESS
					NOP
RGB1W_BYTE_NX:		BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,7	;BIT SFR_INDIR_PORT2.7
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,6	;BIT SFR_INDIR_PORT2.6
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,5	;BIT SFR_INDIR_PORT2.5
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,4	;BIT SFR_INDIR_PORT2.4
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,3	;BIT SFR_INDIR_PORT2.3
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,2	;BIT SFR_INDIR_PORT2.2
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,1	;BIT SFR_INDIR_PORT2.1
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT0	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,0	;BIT SFR_INDIR_PORT2.0
					BC    SFR_PORT_IO,SB_PORT_OUT0	;BIT0
					CALL  RGB1W_DLY_HALF_B0	;APPEND 584n FOR HIGH/LOW
					MOV   SFR_INDIR_PORT2,A	;INCREASE ADDRESS
					BC    SFR_PORT_IO,SB_PORT_OUT0	;FALL EDGE
					CALL  RGB1W_DLY_1L_B0	;LOW 292n IF 1

					DEC   SFR_INDIR_ADDR
					JNZ   RGB1W_BYTE_NX		;NEXT BYTE
RGB1W_LOAD:			MOVL  30
					CALL  DELAY_US			;OUTPUT LOW 286US
;					MOVL  0
					CALL  DELAY_US
					CLRA					;SUCCESS CODE
					BTSC  SFR_PORT_IO,SB_PORT_IN0
					MOVL  0X04				;ERROR CODE IF PIN HIGH
CMD_RETURN:			MOVA  SFR_CTRL_RD		;RETURN RESULT
					BS    SFR_SYS_CFG,SB_INT_REQ	;REQUEST INTERRUPT
					JMP   WAIT_COMMAND
RGB1W_END:			MOVL  0X02				;ERROR CODE IF PARAMETER ERROR
					JMP   CMD_RETURN
;
; RGB WITH SHORT DATA IN SFR, SOFTWARE ENCODE
RGB1W_SHORT_1:		NOP
					BC    SFR_INDIR_ADDR2,6
					CLR   SFR_BIT_CYCLE
					BC    SFR_PORT_IO,SB_PORT_OUT1	;DEFAULT OUTPUT LOW
					BS    SFR_PORT_DIR,SB_PORT_DIR1
					CLR   SFR_BIT_CONFIG
					MOVL  0X06				;ERROR CODE FOR PIN RX HIGH
					BTSC  SFR_PORT_IO,SB_PORT_IN1	;PIN LOW
					JMP   CMD_RETURN		;PIN HIGH
					MOV   SFR_INDIR_ADDR2,A
					MOVA  SFR_INDIR_ADDR	;TOTAL BYTE
					MOVIA SFR_DATA_REG0		;DATA BUFFER START ADDRESS
					NOP
RGB1W_BYTE_NX_1:	BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,7	;BIT SFR_INDIR_PORT2.7
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,6	;BIT SFR_INDIR_PORT2.6
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,5	;BIT SFR_INDIR_PORT2.5
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,4	;BIT SFR_INDIR_PORT2.4
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,3	;BIT SFR_INDIR_PORT2.3
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,2	;BIT SFR_INDIR_PORT2.2
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,1	;BIT SFR_INDIR_PORT2.1
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_INDIR_PORT2,0	;BIT SFR_INDIR_PORT2.0
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF_B0	;APPEND 584n FOR HIGH/LOW
					MOV   SFR_INDIR_PORT2,A	;INCREASE ADDRESS
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L_B0	;LOW 292n IF 1

					DEC   SFR_INDIR_ADDR
					JNZ   RGB1W_BYTE_NX_1		;NEXT BYTE
RGB1W_LOAD_1:		MOVL  30
					CALL  DELAY_US			;OUTPUT LOW 286US
;					MOVL  0
					CALL  DELAY_US
					CLRA					;SUCCESS CODE
					BTSC  SFR_PORT_IO,SB_PORT_IN1
					MOVL  0X04				;ERROR CODE IF PIN HIGH
					JMP   CMD_RETURN
;
; RGB WITH LONG DATA IN CODE RAM, USE PWM DUTY ENCODE
RGB1W_LONG:			NOP
					BTSC  VAR_FLAG,0
					JMP   RGB1W_LONG_1
					CLR   SFR_BIT_CYCLE
					BC    SFR_PORT_IO,SB_PORT_OUT0	;DEFAULT OUTPUT LOW
					MOVL  0X80
					MOVA  SFR_BIT_CONFIG	;SB_BIT_TX_EN
;					BS    SFR_BIT_CONFIG,SB_BIT_TX_EN	;ENABLE TX
					MOV   VAR_SIZE_L,A
					IOR   VAR_SIZE_H,A
					JZ    RGB1W_END			;DATA SIZE IS ZERO
;					BTSS  SFR_PORT_IO,SB_PORT_OUT0	;PIN HIGH
;					JMP   RGB1W_PIN_LOW		;PIN LOW
;					BS    SFR_BIT_CYCLE,6	;FORCE COUNT
;					NOP
;					CLR   SFR_BIT_CYCLE
;					BC    SFR_PORT_IO,SB_PORT_OUT0	;DEFAULT OUTPUT LOW
;					BS    SFR_PORT_DIR,SB_PORT_DIR0
;					CALL  DELAY_65US		;OUTPUT LOW 321US
;					MOVL  0
;					CALL  DELAY_US
;					MOVL  0X05				;ERROR CODE FOR PIN TX HIGH
;					BTSC  SFR_PORT_IO,SB_PORT_OUT0	;PIN LOW
;					JMP   CMD_RETURN		;PIN HIGH
RGB1W_PIN_LOW:		BS    SFR_PORT_DIR,SB_PORT_DIR0
					BC    SFR_INDIR_ADDR2,7	;LOW 7 BIT IS NEW SB_BIT_CYCLE
					CLR   VAR_ADDR_L
					CLR   SFR_INDIR_ADDR
					MOVL  0X06				;ERROR CODE FOR PIN RX HIGH
					BTSC  SFR_PORT_IO,SB_PORT_IN0	;PIN LOW
					JMP   CMD_RETURN		;PIN HIGH
					MOVL  0X02
					MOVA  VAR_ADDR_H		;DATA BUFFER START ADDRESS
					RDCODE					;GET FIRST WORD
					MOVA  SFR_DATA_EXCH		;LOW BYTE
					ANDL  0X80				;FIRST BIT
					IOR   SFR_INDIR_ADDR2,A	;1167nS,0x38(56)@48MHz,0x1C(28)@24MHz
					NOP
					MOVA  SFR_BIT_CYCLE		;SB_BIT_TX_O0=SFR_DATA_EXCH.7...
;					BP2F  BO_BIT_TX_O0,7	;SB_BIT_TX_O0=SFR_DATA_EXCH.7...
RGB1W_WORD_NEXT:	WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,6	;SB_BIT_TX_O0=SFR_DATA_EXCH.6...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,5	;SB_BIT_TX_O0=SFR_DATA_EXCH.5...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,4	;SB_BIT_TX_O0=SFR_DATA_EXCH.4...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,3	;SB_BIT_TX_O0=SFR_DATA_EXCH.3...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,2	;SB_BIT_TX_O0=SFR_DATA_EXCH.2...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					DEC   VAR_SIZE_L
					INC   VAR_SIZE_L,A
					BTSC  SFR_STATUS_REG,SB_FLAG_Z
					DEC   VAR_SIZE_H		;CARRY IF LOW BYTE IS 0XFF
					BP2F  BO_BIT_TX_O0,1	;SB_BIT_TX_O0=SFR_DATA_EXCH.1...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					MOV   VAR_SIZE_L,A
					IOR   VAR_SIZE_H,A
					JZ    RGB1W_BIT_LAST	;FINISH AFTER LAST BIT
					BP2F  BO_BIT_TX_O0,0	;SB_BIT_TX_O0=SFR_DATA_EXCH.0...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
; HIGH BYTE
					MOV   SFR_INDIR_ADDR,A
					MOVA  SFR_DATA_EXCH		;HIGH BYTE
					BP2F  BO_BIT_TX_O0,7	;SB_BIT_TX_O0=SFR_DATA_EXCH.7...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,6	;SB_BIT_TX_O0=SFR_DATA_EXCH.6...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,5	;SB_BIT_TX_O0=SFR_DATA_EXCH.5...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					BP2F  BO_BIT_TX_O0,4	;SB_BIT_TX_O0=SFR_DATA_EXCH.4...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					DEC   VAR_SIZE_L
					INC   VAR_SIZE_L,A
					BTSC  SFR_STATUS_REG,SB_FLAG_Z
					DEC   VAR_SIZE_H		;CARRY IF LOW BYTE IS 0XFF
					BP2F  BO_BIT_TX_O0,3	;SB_BIT_TX_O0=SFR_DATA_EXCH.3...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					INC   VAR_ADDR_L
					BTSC  SFR_STATUS_REG,SB_FLAG_Z
					INC   VAR_ADDR_H		;CARRY IF LOW BYTE IS ZERO
					BP2F  BO_BIT_TX_O0,2	;SB_BIT_TX_O0=SFR_DATA_EXCH.2...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					MOV   VAR_ADDR_L,A
					MOVA  SFR_INDIR_ADDR
					BP2F  BO_BIT_TX_O0,1	;SB_BIT_TX_O0=SFR_DATA_EXCH.1...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					MOV   VAR_SIZE_L,A
					IOR   VAR_SIZE_H,A
					JZ    RGB1W_BIT_LAST	;FINISH AFTER LAST BIT
					MOV   VAR_ADDR_H,A
					BP2F  BO_BIT_TX_O0,0	;SB_BIT_TX_O0=SFR_DATA_EXCH.0...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE AND CLEAR EDGE FLAG AFTER EXIT
					RDCODE					;GET NEXT WORD
					MOVA  SFR_DATA_EXCH		;LOW BYTE
					BP2F  BO_BIT_TX_O0,7	;SB_BIT_TX_O0=SFR_DATA_EXCH.7...
					JMP   RGB1W_WORD_NEXT	;NEXT WORD
RGB1W_BIT_LAST:		BP2F  BO_BIT_TX_O0,0	;SB_BIT_TX_O0=SFR_DATA_EXCH.0...
					WAITB WB_PORT_I0_RISE	;WAIT RISE EDGE OF LAST BIT AND CLEAR EDGE FLAG AFTER EXIT
					BC    SFR_BIT_CYCLE,SB_BIT_TX_O0	;CLEAR FALL EDGE FLAG
					WAITB WB_PORT_I0_FALL	;WAIT FALL EDGE OF LAST BIT AND CLEAR EDGE FLAG AFTER EXIT
					CLR   SFR_BIT_CYCLE		;STOP
;					BC    SFR_BIT_CONFIG,SB_BIT_TX_EN	;ENABLE TX
					JMP   RGB1W_LOAD		;LOAD AND RESET
;
; RGB WITH LONG DATA IN CODE RAM, USE PWM DUTY ENCODE
RGB1W_LONG_1:		NOP
					CLR   SFR_BIT_CYCLE
					CLR   SFR_BIT_CONFIG
					BC    SFR_PORT_IO,SB_PORT_OUT1	;DEFAULT OUTPUT LOW
					MOV   VAR_SIZE_L,A
					IOR   VAR_SIZE_H,A
					JZ    RGB1W_END			;DATA SIZE IS ZERO+
					BS    SFR_PORT_DIR,SB_PORT_DIR1
					CLR   VAR_ADDR_L
					CLR   SFR_INDIR_ADDR
					MOVL  0X06				;ERROR CODE FOR PIN RX HIGH
					BTSC  SFR_PORT_IO,SB_PORT_IN0	;PIN LOW
					JMP   CMD_RETURN		;PIN HIGH
					MOVL  0X02
					MOVA  VAR_ADDR_H		;DATA BUFFER START ADDRESS
					RDCODE					;GET FIRST WORD
					MOVA  SFR_DATA_EXCH		;LOW BYTE

RGB1W_WORD_NEXT_1:	BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,7	;BIT SFR_DATA_EXCH.7
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,6	;BIT SFR_DATA_EXCH.6
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,5	;BIT SFR_DATA_EXCH.5
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,4	;BIT SFR_DATA_EXCH.4
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,3	;BIT SFR_DATA_EXCH.3
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,2	;BIT SFR_DATA_EXCH.2
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,1	;BIT SFR_DATA_EXCH.1
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,0	;BIT SFR_DATA_EXCH.0
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					NOP
					NOP
					NOP
					NOP

					DEC   VAR_SIZE_L
					INC   VAR_SIZE_L,A
					BTSC  SFR_STATUS_REG,SB_FLAG_Z
					DEC   VAR_SIZE_H		;CARRY IF LOW BYTE IS 0XFF
					MOV   VAR_SIZE_L,A
					IOR   VAR_SIZE_H,A
					JZ    RGB1W_LOAD_1	;FINISH AFTER LAST BIT
					MOV   SFR_INDIR_ADDR,A
					MOVA  SFR_DATA_EXCH		;HIGH BYTE

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,7	;BIT SFR_DATA_EXCH.7
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,6	;BIT SFR_DATA_EXCH.6
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,5	;BIT SFR_DATA_EXCH.5
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,4	;BIT SFR_DATA_EXCH.4
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,3	;BIT SFR_DATA_EXCH.3
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,2	;BIT SFR_DATA_EXCH.2
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					CALL  RGB1W_DLY_1L		;LOW 292n IF 1

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,1	;BIT SFR_DATA_EXCH.1
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					NOP
					NOP
					NOP
					NOP

					DEC   VAR_SIZE_L
					INC   VAR_SIZE_L,A
					BTSC  SFR_STATUS_REG,SB_FLAG_Z
					DEC   VAR_SIZE_H		;CARRY IF LOW BYTE IS 0XFF
					INC   VAR_ADDR_L
					BTSC  SFR_STATUS_REG,SB_FLAG_Z
					INC   VAR_ADDR_H		;CARRY IF LOW BYTE IS ZERO
					MOV   VAR_ADDR_L,A
					MOVA  SFR_INDIR_ADDR

					BS    SFR_PORT_IO,SB_PORT_OUT1	;RISE EDGE
					CALL  RGB1W_DLY_0H		;HIGH 292n IF 0
					BTSS  SFR_DATA_EXCH,0	;BIT SFR_DATA_EXCH.0
					BC    SFR_PORT_IO,SB_PORT_OUT1	;BIT0
					CALL  RGB1W_DLY_HALF	;APPEND 584n FOR HIGH/LOW
					BC    SFR_PORT_IO,SB_PORT_OUT1	;FALL EDGE
					NOP
					NOP
					NOP
					NOP
					MOV   VAR_SIZE_L,A
					IOR   VAR_SIZE_H,A
					JZ    RGB1W_LOAD_1		;FINISH AFTER LAST BIT
					MOV   VAR_ADDR_H,A
					RDCODE					;GET NEXT WORD
					MOVA  SFR_DATA_EXCH		;LOW BYTE
					JMP   RGB1W_WORD_NEXT_1	;NEXT WORD
;
; DELAY 250US
DELAY_250US:		MOVL  250
					JMP   DELAY_US
; DELAY 65US
DELAY_65US:			MOVL  65
					JMP   DELAY_US
; DELAY 2US
DELAY_2US:			MOVL  2
; DELAY US
DELAY_US:			CALL  RGB1W_DLY_1L_B0	;10 CLOCK @48M, 4 CLOCK @24M
					NOP
					CALL  RGB1W_DLY_1L_B0	;10 CLOCK @48M, 4 CLOCK @24M
					NOP
					CALL  RGB1W_DLY_1L_B0	;10 CLOCK @48M, 4 CLOCK @24M
					NOP
					CALL  RGB1W_DLY_1L_B0	;10 CLOCK @48M, 4 CLOCK @24M
					NOP
					ADDL  0XFF
					NOP
					JNZ   DELAY_US
					RET
;
; initial DS1W
; OUTPUT: A & Z
INIT_DS1W:			BC    SFR_PORT_DIR,SB_PORT_DIR0	;PULLUP
					CLR   SFR_BIT_CYCLE
					CLR   SFR_BIT_CONFIG
					MOVL  5
					CALL  DELAY_US
					BC    SFR_PORT_IO,SB_PORT_OUT0
					BS    SFR_PORT_DIR,SB_PORT_DIR0	;LOW
					CALL  DELAY_250US	;DELAY >480uS
					CALL  DELAY_250US
					BC    SFR_PORT_DIR,SB_PORT_DIR0	;PULLUP
					CALL  DELAY_65US
					CLR   SFR_INDIR_ADDR2	;ACK
					BTSC  SFR_PORT_IO,SB_PORT_IN0
					MOVIA 0X04				;ERROR CODE IF NAK
					CALL  DELAY_250US
					MOV   SFR_INDIR_ADDR2,A
					RET
; write a byte
; INPUT: A
WRITE_DS1W:			MOVA  SFR_INDIR_ADDR2	;DATA BYTE
					MOVIP 8
WRITE_DS1W_BIT:		BC    SFR_PORT_IO,SB_PORT_OUT0
					BS    SFR_PORT_DIR,SB_PORT_DIR0	;LOW TO START
					CALL  DELAY_2US
					BTSC  SFR_INDIR_ADDR2,0			;BIT DATA 0
					BC    SFR_PORT_DIR,SB_PORT_DIR0	;PULLUP IF BIT DATA 1
					CALL  DELAY_65US
					BC    SFR_PORT_DIR,SB_PORT_DIR0	;PULLUP
					MOVL  5
					BTSS  SFR_INDIR_ADDR2,0			;SKIP DELAY IF BIT DATA 1
					CALL  DELAY_US					;PULLUP FOR BIT DATA 0
					RCR   SFR_INDIR_ADDR2
					DEC   SFR_INDIR_ADDR
					JNZ   WRITE_DS1W_BIT			;8BIT
					RET
; read a byte
; OUTPUT: A
READ_DS1W:			MOVIP 8
READ_DS1W_BIT:		BC    SFR_PORT_IO,SB_PORT_OUT0
					BS    SFR_PORT_DIR,SB_PORT_DIR0	;LOW TO START
					CALL  DELAY_2US
					BC    SFR_PORT_DIR,SB_PORT_DIR0	;PULLUP FOR INPUT
					MOVL  10
					CALL  DELAY_US					;WAIT DATA READY
					RCR   SFR_INDIR_ADDR2
					BC    SFR_INDIR_ADDR2,7
					BTSC  SFR_PORT_IO,SB_PORT_IN0	;GET BIT DATA 0
					BS    SFR_INDIR_ADDR2,7			;GET BIT DATA 1
					MOVL  55
					CALL  DELAY_US					;WAIT SLOT
					DEC   SFR_INDIR_ADDR
					JNZ   READ_DS1W_BIT
					MOV   SFR_INDIR_ADDR2,A
					RET
; start temperature
; OUTPUT: A & Z
START_TEMPERAT:		CALL  INIT_DS1W
					JNZ   START_TEMP_ERR
					MOVL  0XCC						;SKIP ROM
					CALL  WRITE_DS1W
					MOVL  0X44						;CONVERT
					CALL  WRITE_DS1W
					BTSS  SFR_SYS_CFG,SB_MST_CFG_B4	;PARASITE POWER
					JMP   START_TEMP_RET			;EXTERNAL POWER
					BS    SFR_PORT_IO,SB_PORT_OUT0
					BS    SFR_PORT_DIR,SB_PORT_DIR0	;HIGH FOR POWER
START_TEMP_RET:		CLRA
START_TEMP_ERR:		RET
; read temperature
; OUTPUT: VAR_DATA_L/H
READ_TEMPERAT:		CALL  INIT_DS1W
					JNZ   READ_TEMP_ERR
					MOVL  0XCC						;SKIP ROM
					CALL  WRITE_DS1W
					MOVL  0XBE						;READ DATA
					CALL  WRITE_DS1W
					CALL  READ_DS1W
					MOVA  VAR_DATA_L				;LOW BYTE
					CALL  READ_DS1W
					MOVA  VAR_DATA_H				;HIGH BYTE
					CALL  INIT_DS1W
READ_TEMP_ERR:		RET
;
					NOP
;
END
;
